Finite State Machine (FSM) - VHDL

Notes: This program implements a three-state Finite State Machine (FSM) with the following details:
STATE A: Stays on state A on reset, second bit doesn't matter; first bit 0 -> State B, first bit 1 -> State C
STATE B: Goes to state A on reset; on clock, goes to State C no matter what
STATE C: Goes to state A on reset, first bit doesn't matter; second bit 1 -> State A, second bit 0 -> State C
Bits are determined by switches 1 and 0 respectively. Clock is a button.

This VHDL code was written for an Artix-7 family Nexys 4 FPGA board. Constraints file can be downloaded by clicking HERE or in the GitHub repository.

The following code was written as part of coursework for University of Mississippi class EL E 386 (Advanced Digital Systems Lab).

You can also view and download the code by visiting the GitHub repository HERE.

Disclaimer: All of this code is listed here as samples of the work I've done both inside and outside of the classroom here at Ole Miss. Many of these coding samples were done as part of a project for a class I belonged to, or were done for my own personal practice from other years' programming assignments; if this is the case, I have labeled it with the relevant University of Mississippi course number. My code may or may not be correct- it is simply posted with the intent to serve as a demonstration of my growth over time as a programmer, and for the work to serve as a guide to other programmers who are attempting to learn the craft themselves. I DO NOT recommend copying any of my code verbatim under any circumstances due to the risk of academic disciplinary measures being taken against you, and I am NOT responsible if this or any other negative result occurs from use of my code. Using or viewing this code in any way constitutes an affirmation that you have read and consent to this disclaimer, and to the terms of the provided GNU AGPLv3 License. The full license can be found HERE.